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3-33 august 1997 ICL7139, icl7149 3 3 / 4 digit, autoranging multimeter features ? 13 ranges - ICL7139 - 4 dc voltage 400mv, 4v, 40v, 400v - 1 ac voltage 400v - 4 dc current 4ma, 40ma, 400ma, 4a - 4 resistance 4k w , 40k w , 400k w , 4m w ? 18 ranges - icl7149 - 4 dc voltage 400mv, 4v, 40v, 400v - 2 ac voltage with optional ac circuit - 4 dc current 4ma, 40ma, 400ma, 4a - 4 ac current with optional ac circuit - 4 resistance 4k w , 40k w , 400k w , 4m w ? autoranging - first reading is always on correct range ? on-chip duplex lcd display drive including three dec- imal points and 11 annunciators ? no additional active components required ? low power dissipation - less than 20mw - 1000 hour typical battery life ? display hold input ? continuity output drives piezoelectric beeper ? low battery annunciator with on-chip detection ? guaranteed zero reading for 0v input on all ranges description the intersil ICL7139 and icl7149 are high performance, low power, auto-ranging digital multimeter lcs. unlike other autoranging multimeter ics, the ICL7139 and icl7149 always display the result of a conversion on the correct range. there is no range hunting noticeable in the display. the unit will autorange between the four different ranges. a manual switch is used to select the 2 high group ranges. dc current ranges are 4ma and 40ma in the low current group, and 400ma and 4a in the high current group. resistance measurements are made on 4 ranges, which are divided into two groups. the low resistance ranges are 4/40k w . the high resistance ranges are 0.4/4m w . resolution on the lowest range is 1 w . pinouts ordering information part number temp. range ( o c) package pkg. no. ICL7139cpl 0 to 70 40 ld pdip e40.6 icl7149cpl 0 to 70 40 ld pdip e40.6 icl7149cm44 0 to 70 44 ld mqfp q44.10x10 ICL7139, icl7149 (pdip) top view icl7149 (mqfp) top view 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 pol/ac bp2 bp1 v+ v- v ref lo w hi w deint common int 1 int v/ w triple point c az c int beeper out ma/ m a v/ w /a h i w -dc/lo w -ac hold 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 adg 3 /e 3 b 3 /c 3 f 2 /dp 3 g 2 /e 2 a 2 /d 2 b 2 /c 2 f 1 /dp 2 g 1 /e 1 a 1 /d 1 b 1 /c 1 f 0 /dp 1 g 0 /e 0 a 0 /d 0 b 0 /c 0 lo bat/v m w / m a w /a k/m osc in osc out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 28 27 26 25 24 23 22 21 20 19 18 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 m w / m a w /a k/m osc in osc out hold beeper out ma/ m a v/ w /a hi w -dc/lo w -ac nc adg 3 /e 3 b 3 /c 3 f 2 /dp 3 g 2 /e 2 a 2 /d 2 pol/ac nc bp2 bp1 v+ nc v- v ref lo w hi w deint common int 1 int v/ w triple point c az c int b 2 /c 2 f 1 /dp 2 g 1 /e 1 a 1 /d 1 b 1 /c 1 f 0 /dp 1 g 0 /e 0 a 0 /d 0 b 0 /c 0 nc lo bat/v file number 3088.1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
3-34 functional block diagram control logic including autoranging logic analog section analog switches, integration and comparator power supply section beeper driver osc counters display driver and latches display digital common switches crystal v+ v- com piezo electric beeper external resistors and capacitors ICL7139, icl7149
3-35 absolute maximum ratings thermal information supply voltage (v+ to v-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15v reference input voltage (v ref to com) . . . . . . . . . . . . . . . . . . . 3v analog input current (in + current or in + voltage) . . . . . . . 100 m a clock input swing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v+ to v+ -3 operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 o c to 70 o c thermal resistance (typical, note 1) q ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (mqfp - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 1. q ja is measured with the component mounted on an evaluation pc board in free air. electrical speci?cations v+ = 9v, t a = 25 o c, v ref adjusted for -3.700 reading on dc volts, test circuit as shown in figure 3. crystal = 120khz. (see figure 14) parameter test conditions min typ max units zero input reading v in or i in or r in = 0.00 -00.0 - +00.0 v, i, w linearity (best straight line) (note 6) (notes 1 and 8) -1 - +1 counts accuracy dc v, 400v range only (notes 1 and 8) - - 1 % of rdg 1 accuracy dc v, 400v range excluded (notes 1 and 8) - - 0.30 % of rdg 1 accuracy w , 4k and 400k range (notes 1 and 8) - - 0.75 % of rdg 8 accuracy w , 4k and 4m range (notes 1 and 8) - - 1 % of rdg 9 accuracy dc i, unadjusted for full scale (notes 1 and 8) - - 0.75 % of rdg 1 accuracy dc i, adjusted for full scale (notes 1 and 8) - 0.2 - % of rdg 1 accuracy ac v at 60hz (notes 5, 7, and 8) - 2 - % of rdg open circuit voltage for w measurements r unknown = infinity - v ref -v noise v in = 0, dc v (note 2, 95% of time) - 0.1 - lsb noise v in = 0, ac v (note 2, 95% of time) - 4 - lsb supply current v in = 0, dc voltage range - 1.5 2.4 ma analog common (with respect to v+) i common < 10 m a 2.7 2.9 3.1 v temperature coefficient of analog common i common < 10 m a, temp. = 0 o c to 70 o c - -100 - ppm/ o c output impedance of analog common i common < 10 m a-110 w backplane/segment drive voltage average dc < 50mv 2.8 3.0 3.2 v backplane/segment display frequency - 75 - hz switch input current v in = v+ to v- (note 3) -50 - +50 m a switch input levels (high trip point) v+ - 0.5 - v+ v switch input levels (mid trip point) v- + 3 - v+ - 2.5 v switch input levels (low trip point) v- - v- + 0.5 v beeper output drive (rise or fall time) c load = 10nf - 25 100 m s beeper output frequency - 2 - khz continuity detect range = low w , v ref = 1.00v - 1.5 - k w power supply functional operation v+ to v- 7 9 11 v low battery detect v+ to v- (note 4) 6.5 7 7.5 v notes: 1. accuracy is de?ned as the worst case deviation from ideal input value including: offset, linearity, and rollover error. 2. noise is defined as the width of the uncertainty window (where the display will flicker) between two adjacent codes. 3. applies to pins 17-20. 4. analog common falls out of regulation when the low battery detect is asserted, however the ICL7139 and icl7149 will continue to operate correctly with a supply voltage above 7v and below 11v. 5. for 50hz use a 100khz crystal. 6. guaranteed by design, not tested. 7. ICL7139 only. 8. rdg = reading. ICL7139, icl7149
3-36 timing waveform pin descriptions first deintegrate underrange auto zero underrange underrange auto zero auto zero second auto zero fourth auto zero auto zero second integrate second deintegrate third auto zero third integrate third deintegrate fourth integrate fourth deintegrate 0123456789101112131415161718192021222324 first auto zero first integrate figure 1. line frequency cycles (1 cycle = 1000 internal clock pulses = 2000 oscillation cycles) i/o pin number description o 1 segment driver pol/ac o 2 backplane 2 o 3 backplane 1 i4v+ i5v- i 6 reference input o7lo w o8hi w i/o 9 deintegrate i/o 10 analog common i 11 int i i 12 int v/ w i 13 triple point i 14 auto zero capacitor (c az ) i 15 integrate capacitor (c int ) o 16 beeper output i17ma/ m a i18 w /v/a i19hi w dc/lo w ac i 20 hold o 21 oscillator out i 22 oscillator in o 23 segment driver k/m o 24 segment driver w /a o 25 segment driver m w / m a o 26 segment driver lo bat/v o 27 segment driver b 0 /c 0 o 28 segment driver a 0 /d 0 o 29 segment driver g 0 /e 0 o 32 segment driver a 1 /d 1 o 33 segment driver g 1 /e 1 o 34 segment driver f 1 /dp 1 o 35 segment driver b 2 /c 1 o 39 segment driver b 3 /c 3 o 40 segment driver adg 3 /e 3 note: for segment drivers, segments are listed as (segment for backplane 1)/(segment for backplane 2). example: pin 27; segment b 0 is on backplane 1, segment c 0 is on backplane 2. i/o pin number description ICL7139, icl7149
3-37 detailed description general the functional block diagram shows the digital section which includes all control logic, counters, and display drivers. the digital section is powered by v+ and digital common, which is about 3v below v+. the oscillator is also in the digi- tal section. normally 120khz for rejection of 60hz ac inter- ference and 100khz for rejection of 50hz ac should be used. the oscillator output is divided by two to generate the internal master clock. the analog section contains the inte- grator, comparator, reference section, analog buffers, and several analog switches which are controlled by the digital logic. the analog section is powered from v+ and v-. dc voltage measurement autozero only those portions of the analog section which are used during dc voltage measurements are shown in figure 3. as shown in the timing diagram (figure 1), each measurement starts with an autozero (az) phase. during this phase, the integrator and comparator are con?gured as unity gain buff- ers and their non-inverting inputs are connected to common. the output of the integrator, which is equal to its offset, is stored on c az - the autozero capacitor. similarly, the offset of the comparator is stored in c lnt . the autozero cycle equals 1000 clock cycles which is one 60hz line cycle with a 120khz oscillator, or one 50hz line cycle with a 100khz oscillator. range 1 integrate the ICL7139 and icl7149 perform a full autorange search for each reading, beginning with range 1. during the range 1 integrate period, internal switches connect the int v/ w terminal to the triple point (pin 13). the input signal is inte- grated for 10 clock cycles, which are gated out over a period of 1000 clock cycles to ensure good normal mode rejection of ac line interference. low batt digit 3 2 1 0 dp3 dp2 dp1 ac a b k w m w c mav m a g d e f figure 2. display segment nomenclature + - + - + - triple point c az c int r deint az deint - deint- v ref integrator comparator to logic section 6.7v analog v in r intv int v/ w 80 m a c az c int r deint az az az common t t deint+ deint+ v+ v- t = (int)(ar)( az) ar = autorange chopper az = autozero int = integrate v ref common figure 3. detailed circuit diagram for dc voltage measurement ICL7139, icl7149
3-38 range 1 deintegrate at the beginning of the deintegrate cycle, the polarity of the voltage on the integrator capacitor (c int ) is checked, and either the delnt+ or delnt- is asserted. the integrator capacitor c int is then discharged with a current equal to v ref /r delnt . the comparator monitors the voltage on c int . when the voltage on c int is reduced to zero (actually to the v os of the comparator), the comparator output switches, and the current count is latched. if the c int voltage zero-crossing does not occur before 4000 counts have elapsed, the over- load ?ag is set. ol (overload) is then displayed on the lcd. if the latched result is between 360 and 3999, the count is trans- ferred to the output latches and is displayed. when the count is less than 360, an underrange has occurred, and the ICL7139 and icl7149 then switch to range 2 - the 40v scale. range 2 the range 2 measurement begins with an autozero cycle similar to the one that preceded range 1 integration. range 2 cycle length however, is one ac line cycle, minus 360 clock cycles. when performing the range 2 cycle, the signal is inte- grated for 100 clock cycles, distributed throughout one line cycle. this is done to maintain good normal mode rejection. range 2 sensitivity is ten times greater than range 1 (100 vs 10 clock cycle integration) and the full scale voltage of range 2 is 40v. the range 2 deintegrate cycle is identical to the range 1 deintegrate cycle, with the result being displayed only for readings greater than 360 counts. if the reading is below 360 counts, the ICL7139 and icl7149 again asserts the internal underrange signal and proceeds to range 3. range 3 the range 3v or 4v full scale measurement is identical to the range 2 measurement, except that the input signal is inte- grated during the full 1000 clock cycles (one line frequency cycle). the result is displayed if the reading is greater than 360 counts. underrange is asserted, and a range 4 measure- ment is performed if the result is below 360 counts. range 4 this measurement is similar to the range 1, 2 and 3 mea- surements, except that the integration period is 10,000 clock cycles (10 line cycles) long. the result of this measurement is transferred to the output latches and displayed even if the reading is less than 360. autozero after ?nding the ?rst range for which the reading is above 360 counts, the display is updated and an autozero cycle is entered. the length of the autozero cycle is variable which results in a ?xed measurement period of 24,000 clock cycles (24 line cycles). dc current figure 4 shows a simpli?ed block diagram of the analog section of the ICL7139 and icl7149 during dc current measurement. the dc current measurements are very similar to dc voltage measurements except: 1) the input voltage is developed by passing the input current through a 0.1 w (hi current ranges), or 9.9 w (low current ranges) + - + - + - triple point c az c int r deint az deint - deint- v ref integrator comparator to logic section 6.7v analog low i r inti int i 80 m a c az c int r deint az az az common t t deint+ deint+ v+ v- t = (int)(ar)( az) ar = autorange chopper az = autozero int = integrate v ref 9.9 w 0.1 w high i i common figure 4. detailed circuit diagram for dc current measurement ICL7139, icl7149
3-39 current sensing resistor; 2) only those ranges with 1000 and 10,000 clock cycles of integration are used; 3) the r lnt l resistor is 1m w , rather than the 10m w value used for the r lnt v resistor. by using the lower value integration resistor, and only the 2 most sensitive ranges, the voltage drop across the current sensing resistor is 40mv maximum on the 4ma and 400ma ranges; 400mv maximum on the 40ma and 4a scales. with some increase in noise, these burden voltages can be reduced by lowering the value of both the current sense resistors and the r lnt l resistor proportionally. the dc current measurement timing diagram is similar to the dc voltage measurement timing diagram, except in the dc current timing diagram, the ?rst and second integrate and deintegrate phases are skipped. ac voltage measurement for ICL7139 as shown in figure 5, the ac input voltage is applied directly to the ICL7139 input resistor. no separate ac to dc conver- sion circuitry is needed. the ac measurement cycle is begun by disconnecting the integrator capacitor and using the integrator as an autozeroed comparator to detect the positive-going zero crossing. once synchronized to the ac input, the autozero loop is closed and a normal integrate/deintegrate cycle begins. the ICL7139 resynchro- nizes itself to the ac input prior to every reading. because diode d4 is in series with the integrator capacitor, only posi- tive current from the integrator ?ows into the integrator capacitor, c lnt . since the voltage on c lnt is proportional to the half-wave recti?ed average ac input voltage, a conver- sion factor must be applied to convert the reading to rms. this conversion factor is p /2 ? 2 = 1.1107, and the system clock is manipulated to perform the rms conversion. as a result the deintegrate and autozero cycle times are reduced by 10%. ac voltage measurement for icl7149 the icl7149 is designed to be used with an optional ac to dc voltage converter circuit. it will autorange through two voltage ranges (400v and 40v), and the ac annunciator is enabled. a typical averaging ac to dc converter is shown in figure 6, while an rms to dc converter is shown in figure 7. ac current can also be measured with some simple modi- ?cations to either of the two circuits in figures 6 and 7. + - + - + - triple point c az c int az deint deint- v ref integrator comparator 6.7v common r intv int v/ w 80 m a c az deint az az ~ t t v+ v- t = (int + acs) az ar ar = autorange chopper az = autozero int = integrate ac in ~ s = az ? a cs ? a cint acs = ac sync d3 acint d2 acs d1 d4 acint 5 r deint c int acs figure 5. detailed circuit diagram for ac voltage measurement for ICL7139 only ICL7139, icl7149
3-40 figure 6. ac voltage measurement using optional averaging circuit figure 7. ac voltage measurement using optional rms converter circuit icl7652 20m w v in 100k w 50k w v + 4 11 7 10 5 1 8 2 0.1 m f 1.0 m f com 43.2k w 12 full int (v/ w ) icl7149 common - + 20m w 0.1 m f v - icl7652 v + 4 11 7 10 5 1 8 2 0.1 m f - + 0.1 m f v - 100k w 5k w scale adjust 10 0vac - 400vac 0hz - 1000hz ad736 v + 2 7 3 6 8 4 5 10 m f 1 12 int (v/ w ) icl7149 common + + 2.2 m f com full 10m w v - scale adjust 4.99k w 2.2 m f 5k w 30k w 10 v + v in 0vac - 400vac 50hz - 1000hz + ICL7139, icl7149
3-41 ratiometric w measurement the ratiometric w measurement is performed by ?rst integrating the voltage across an unknown resistor, r x , then effectively deintegrating the voltage across a known resistor (r known1 or r known2 of figure 8). the shunting effect of r intv does not affect the reading because it cancels exactly between integration and deintegration. like the current mea- surements, the w measurements are split into two sets of ranges. lo w measurements use a 10k w reference resistor, and the full scale ranges are 4k w and 40k w . hi w measure- ments use a 1m w reference resistor, and the full scale ranges are 0.4m w and 4m w . the measurement phases and timing are the same as the measurement phases and timing for dc current except: 1) during the integrate phases the input volt- age is the voltage across the unknown resistor r x , and; 2) during the deintegrate phases, the input voltage is the voltage across the reference resistor r known1 or r known2 . continuity indication when the ICL7139 and icl7149 are in the lo w measurement mode, the continuity circuit of figure 9 will be active. when the voltage across r x is less than approximately 100mv, the beeper output will be on. when r known is 10k w , the beeper output will be on when r x is less than 1k w . common voltage the analog and digital common voltages of the ICL7139 and icl7149 are generated by an on-chip resistor/zener/diode combination, shown in figure 10. the resistor values are chosen so the coef?cient of the diode voltage cancels the positive temperature coef?cient of the zener voltage. this voltage is then buffered to provide the analog common and the digital common voltages. the nominal voltage between v+ and analog common is 3v. the analog common buffer can sink about 20ma, or source 0.01ma, with an output impedance of 10 w . a pullup resistor to v+ may be used if more sourcing capability is desired. analog common may be used to generate the reference voltage, if desired. oscillator the ICL7139 and icl7149 use a parallel resonant-type crystal in a pierce oscillator con?guration, as shown in figure 11, and requires no other external components. the crystal eliminates the need to trim the oscillator frequency. an external signal may be capacitively coupled in osc in, with a signal level between 0.5v and 3v p-p . because the + - + - + - triple point c az c int r deint az integrator comparator to logic section common r intv int v/ w c az c int r deint az az az t t deint+ deint+ t = int + deint az = autozero int = integrate v ref low w + - lo w w lo w hi w r known 1 r known 2 r x figure 8. detailed circuit diagram for ratiometric w measurement + - com lo w hi w + - + - r known v x beeper output r unknown v ref lo w 2khz v+ v+ v x = 100mv r x figure 9. continuity beeper drive circuit + - p + - p 0.3v + - logic section v+ lo bat digital common (internal) 3.1v + + 3v - analog common (pin 10) v- 6.7v 125k 5k 180k 80 m a figure 10. analog and digital common voltage generator circuit + - ICL7139, icl7149
3-42 osc out pin is not designed to drive large external loads, loading on this pin should not exceed a single cmos input. the oscillator frequency is internally divided by two to gener- ate the ICL7139 and icl7149 clock. the frequency should be 120khz to reject 60hz ac signals, and 100khz to reject 50hz signals. display drivers figure 12 shows typical lcd drive waveforms, rms on, and rms off voltage calculations. duplex multiplexing is used to minimize the number of connections between the ICL7139 and icl7149 and the lcd. the lcd has two separate back- planes. each drive line can drive two individual segments, one referenced to each backplane. the ICL7139 and icl7149 drive 3 3 / 4 7-segment digits, 3 decimal points, and 11 annunci- ators. annunciators are used to indicate polarity, low battery condition, and the range in use. peak drive voltage across the display is approximately 3v. an lcd with approximately 1.4v rms threshold voltage should be used. the third voltage level needed for duplex drive waveforms is generated through an on-chip resistor string. the dc component of the drive waveforms is guaranteed to be less than 50mv. ternary input the w /volts/amps logic input is a ternary, or 3-level input. this input is internally tied to the common voltage through a high-value resistor, and will go to the middle, or volts state, when not externally connected. when connected to v-, approximately 5 m a of current ?ows out of the input. in this case, the logic level is the amps, or low state. when con- nected to v+, about 5 m a of current ?ows into the input. here, the logic level is the w , or high state. for other pins, see table 2. component selection for optimum performance while maintaining the low-cost advantages of the ICL7139 and icl7149, care must be taken when selecting external components. this section reviews speci?cations and performance effects of various external components. 5m 330k 10pf 5pf osc out osc in figure 11. internal oscillator circuit diagram table 2. ternary inputs connections pin number v+ open or com v- 17 ma m a test 18 w v amps 19 hi w /dc lo w /ac test 20 hold auto test backplane segment on segment off v segment on v segment off v peak v peak / 2 o v peak o v peak o 2v peak o (voltage across on segment) (voltage across off segment) -2v peak v peak o -v peak v+ dcom v peak = 3v 10% rms on ? 2.37v rms off ? 1.06v v rms 5 8 -- - v peak on = v rms 5 8 -- - v peak off = figure 12. duplexed lcd drive waveforms ICL7139, icl7149
3-43 integrator capacitor, c lnt as with all dual-slope integrating convertors, the integration capacitor must have low dielectric absorption to reduce linearity errors. polypropylene capacitors add undetectable errors at a reasonable cost, while polystyrene and polycarbonate may be used in less critical applications. the ICL7139 and icl7149 are designed to use a 3.3nf (0.0033 m f) c lnt with an oscillator frequency of 120khz and an r lntv of 10m w . with a 100khz oscillator frequency (for 50hz line frequency rejection), c lnt and r intv affects the voltage swing of the integrator. voltage swing should be as high as possible without saturating the integrator. saturation occurs when the integrator output is within 1v of either v+ or v-. integrator voltage swing should be about 2v when using standard component values. for different r lntv and oscillator frequencies the value of c lnt can be calculated from: integrator resistors the normal values of the r lnt v and r lnt l resistors are 10m w and 1m w respectively. though their absolute values are not critical, unless the value of the current sensing resis- tors are trimmed, their ratio should be 10:1, within 0.05%. some carbon composition resistors have a large voltage coef?cient which will cause linearity errors on the 400v scale. also, some carbon composition resistors are very noisy. the class a output of the integrator begins to have nonlinearities if required to sink more than 70 m a (the sourcing limit is much higher). because r lnt v drives a virtual ground point, the input impedance of the meter is equal to r lnt v . deintegration resistor, r delnt unlike most dual-slope a/d converters, the ICL7139 and icl7149 use different resistors for integration and deintegra- tion. r delnt should normally be the same value as r lnt v , and have the same temperature coef?cient. slight errors in matching may be corrected by trimming the reference voltage. autozero capacitor, c az the c az is charged to the integrators offset voltage during the autozero phases, and subtracts that voltage from the input signal during the integrate phases. the integrator thus appears to have zero offset voltage. minimum c az value is determined by: 1) circuit leakages; 2) c az self-discharge; 3) charge injection from the internal autozero switches. to avoid errors, the c az voltage change should be less than 1/10 of a count during the 10,000 count clock cycle integra- tion period for the 400mv range. these requirements set a lower limit of 0.047 m f for c az but 0.1 m f is the preferred value. the upper limit on the value of c az is set by the time constant of the autozero loop, and the 1 line cycle time period allotted to autozero. c az may be several 10s of m f before approaching this limit. the ideal c az is a low leakage polypropylene or te?on capacitor. other ?lm capacitors such as polyester, polysty- rene, and polycarbonate introduce negligible errors. if a few seconds of settling time upon power-up is acceptable, the c az may be a ceramic capacitor, provided it does not have excessive leakage. ohm measurement resistors because the ICL7139 and icl7149 use a ratiometric ohm measurement technique, the accuracy of ohm reading is pri- marily determined by the absolute accuracy of the r known1 and r known2 . these should normally be 10k w and 1m w , with an absolute accuracy of at least 0.5%. current sensing resistors the 0.1 w and 9.9 w current sensing resistors convert the measured current to a voltage, which is then measured using r lnt l . the two resistors must be closely matched, and the ratio between r lnt l and these two resistors must be accurate - normally 0.5%. the 0.1 w resistor must be capa- ble of handling the full scale current of 4a, which requires it to dissipate 1.6w. continuity beeper the continuity beeper output is designed to drive a piezo- electric transducer at 2khz (using a 120khz crystal), with a voltage output swing of v+ to v-. the beeper output off state is at the v+ rail. when crystals with different frequencies are used, the frequency needed to drive the transducer can be calculated by dividing the crystal frequency by 60. display the ICL7139 and icl7149 use a custom, duplexed drive dis- play with range, polarity, and low battery annunciators. with a 3v peak display voltage, the rms on voltage will be 2.37v minimum; rms off voltage will be 1.06v maximum. because the display voltage is not adjustable, the display should have a 10% on threshold of about 1.4v. most display manufacturers supply a graph that shows contrast versus rms drive voltage. this graph can be used to determine what the contrast ratio will be when driven by the ICL7139 and icl7149. most display thresholds decrease with increasing temperature. the threshold at the maximum operating temperature should be checked to ensure that the off segments will not be turned on at high temperatures. crystal the ICL7139 and icl7149 are designed to use a parallel resonant 120khz or 100khz crystal with no additional exter- nal components. the r s parameter should be less than 25k w to ensure oscillation. initial frequency tolerance of the crystal can be a relatively loose 0.05%. switches because the logic input draws only about 5 m a, switches driving these inputs should be rated for low current, or dry operations. the switches on the external inputs must be able to reliably switch low currents, and be able to handle voltages in excess of 400v ac . c int integrate time () integrate current () desired integrator swing () --------------------------------------------------------------------------------------------------- - = 10,000 x 2 x oscillator period () 0.4v/r intv 2v () ------------------------------------------------------------------------------------------------------------------------- = ICL7139, icl7149
3-44 reference voltage source a voltage divider connected to v+ and common is the sim- plest source of reference voltage. while minimizing external component count, this approach will provide the same volt- age tempco as the ICL7139 and icl7149 common - about 100ppm/ o c. to improve the tempco, an icl8069 bandgap reference may be used (see figure 13). the reference volt- age source output impedance must be r delnt /4000. applications, examples, and hints a complete autoranging 3 3 / 4 digit multimeter is shown in figure 14. the following sections discuss the functions of speci?c components and various options. meter protection the ICL7139 and icl7149 and their external circuitry should be protected against accidental application of 110/220v ac line voltages on the w and current ranges. without the nec- essary precautions, both the ICL7139 and icl7149 and their external components could be damaged under such fault conditions. for the current ranges, fast-blow fuses should be used between s5a in figure 14 and the 0.1 w and 9.9 w shunt resistors. for the w ranges, no additional protection circuitry is required. however, the 10k w resistor connected to pin 7 must be able to dissipate 1.2w or 4.8w for short periods of time during accidental application of 110v or 220v ac line voltages respectively. deintegrate integrate volt/ w integrate current reference input analog common triple point external reference 10m 10k 1m 10m 10k icl8069 v+ figure 13. external voltage reference connection to ICL7139 and icl7149 13 14 15 deint int (v/ w ) common lo w triple 10m w point hi w int (i) v/ w /a ma/ m a ICL7139 icl7149 hold hi w -dc/lo w -ac v ref v- v+ beeper display drive outputs c az c int osc out osc in 1-3 23-40 beeper inputs v/ w s4a v a m a ma s5a 9 12 7 8 11 10 18 17 w common v+ v+ v- m a a v w ma s4b 10k w 1m w 1m w 9.9 w 10m w a 0.1 w 2w 20 s3 19 s3 v+ v+ 6 5 4 16 1 m f on/off s1 9v battery tant 4.7 m f pin 4 icl8069 pin 10 lo bat ac mav m a 10k w 120khz crystal 0.1 m f 3.3nf 21 22 k w m w 30k- 50k + + + - 10k w s2 closed: hi w -dc s3 closed: hold reading notes: 1. crystal is a statek or saronix cx-iv type. 2. multimeter protection components have not been shown. 3. display is from lxd, part number 38d8r02h (or equivalent). 4. beeper is from murata, part number pkm24-4a0 (or equivalent). figure 14. basic multimeter application circuit for ICL7139 and icl7149 ICL7139, icl7149
3-45 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com printed circuit board layout considerations particular attention must be paid to rollover performance, leakages, and guarding when designing the pcb for a ICL7139 and icl7149 based multimeter. rollover performance, leakages, and guarding because the ICL7139 and icl7149 system measures very low currents, it is essential that the pcb have low leakage. boards should be properly cleaned after soldering. areas of particular importance are: 1) the int v/ w and int l pins; 2) the triple point; 3) the r delnt and the c az pins. the conversion scheme used by the ICL7139 and icl7149 changes the common mode voltage on the integrator and the capacitors c az and c lnt during a positive deintegrate cycle. stray capacitance to ground is charged when this occurs, removing some of the charge on c lnt and causing rollover error. rollover error increases about 1 count for each picofarad of capacitance between c az or the triple point and ground, and is seen as a zero offset for positive volt- ages. rollover error is not seen as gain error. the rollover error causes the width of the +0 count to be larger than normal. the ICL7139 and icl7149 will thus read zero until several hundred microvolts are applied in the posi- tive direction. the ICL7139 and icl7149 will read -1 when approximately -100 m v is applied. the rollover error can be minimized by guarding the triple point and c az nodes with a trace connected to the c lnt pin, (see figure 15) which is driven by the output of the integra- tor. guarding these nodes with the output of the integrator reduces the stray capacitance to ground, which minimizes the charge error on c lnt and c az . if possible, the guarding should be used on both sides of the pc board. stray pickup while the ICL7139 and icl7149 have excellent rejection of line frequency noise and pickup in the dc ranges, any stray coupling will affect the ac reading. generally, the analog cir- cuitry should be as close as possible to the ICL7139 and icl7149. the analog circuitry should be removed or shielded from any 120v ac power inputs, and any ac sources such as lcd drive waveforms. keeping the analog circuit section close to the ICL7139 and icl7149 will also help keep the area free of any loops, thus reducing magneti- cally coupled interference coming from power transformers, or other sources. 14 15 13 12 11 10 9 figure 15. pc board layout ICL7139, icl7149

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